Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
In a common IC fabrication technique known as a dual damascene technique, lower and upper dielectric layers are sequentially deposited on a substrate. A via opening is patterned and etched in the lower dielectric layer, and a trench opening is patterned and etched in the upper dielectric layer. At each step, a patterned photoresist layer is used to etch the trench and via openings in the corresponding dielectric layer. A conductive copper line is then formed in the trench and via openings, typically using electrochemical plating (ECP) techniques, to form the horizontal and vertical IC circuit interconnects on the substrate.
Photoresist materials are coated onto the surface of a wafer, or onto a dielectric or conductive layer on a wafer, by dispensing a photoresist fluid typically on the center of the wafer as the wafer rotates at high speeds within a stationary bowl or coater cup. The coater cup catches excess fluids and particles ejected from the rotating wafer during application of the photoresist. The photoresist fluid dispensed onto the center of the wafer is spread outwardly toward the edges of the wafer by surface tension generated by the centrifugal force of the rotating wafer. This facilitates uniform application of the liquid photoresist on the entire surface of the wafer.
During the photolithography step of semiconductor production, light energy is applied through a reticle or mask onto the photoresist material previously deposited on the wafer to define circuit patterns which will be etched in a subsequent processing step to define the circuits on the wafer. A reticle is a transparent plate patterned with a circuit image to be formed in the photoresist coating on the wafer. A reticle contains the circuit pattern image for only a few of the die on a wafer, such as four die, for example, and thus, must be stepped and repeated across the entire surface of the wafer. In contrast, a photomask, or mask, includes the circuit pattern image for all of the die on a wafer and requires only one exposure to transfer the circuit pattern image for all of the dies to the wafer.
Spin coating of photoresist on wafers, as well as the other steps in the photolithography process, is carried out in an automated coater/developer track system using wafer handling equipment which transport the wafers between the various photolithography operation stations, such as vapor prime resist spin coat, develop, baking and chilling stations. Robotic handling of the wafers minimizes particle generation and wafer damage. Automated wafer tracks enable various processing operations to be carried out simultaneously. Two types of automated track systems widely used in the industry are the TEL (Tokyo Electron Limited) track and the SVG (Silicon Valley Group) track.
A typical method of forming a circuit pattern on a wafer includes introducing the wafer into the automated track system and then spin-coating a photoresist layer onto the wafer. The photoresist is next cured by conducting a soft bake process. After it is cooled, the wafer is placed in an exposure apparatus, such as a stepper, which aligns the wafer with an array of die patterns etched on the typically chrome-coated quartz reticle. When properly aligned and focused, the stepper exposes a small area of the wafer, then shifts or “steps” to the next field and repeats the process until the entire wafer surface has been exposed to the die patterns on the reticle. The photoresist is exposed to light through the reticle in the circuit image pattern. Exposure of the photoresist to this image pattern cross-links and hardens the resist in the circuit pattern. After the aligning and exposing step, the wafer is exposed to post-exposure baking and then is developed and hard-baked to develop the photoresist pattern.
The circuit pattern defined by the developed and hardened photoresist is next transferred to an underlying metal layer using an etching process, in which metal in the metal layer not covered by the cross-linked photoresist is etched away from the wafer with the metal under the cross-linked photoresist that defines the device feature protected from the etchant. Alternatively, the etched material may be a dielectric layer in which via openings and trench openings are etched according to the circuit pattern, such as in a dual damascene technique. The via and trench openings are then filled with a conductive metal such as copper to define the metal circuit lines. As a result, a well-defined pattern of metallic microelectronic circuits, which closely approximates the cross-linked photoresist circuit pattern, is formed on the wafer.
FIG. 1A illustrates a semiconductor wafer portion 10 on which a semiconductor IC device feature is being fabricated. The portion 10 includes a substrate 12, a feature layer 14 deposited on the substrate 12, a BARC (bottom anti-reflective coating) layer 18 deposited on the feature layer 14, and a photoresist mask 16 patterned and developed on the BARC layer 18. The photoresist mask 16 may include an organic spin-on photoresist compound that is selectively exposed to deep-UV (DUV) radiation at the patterning and developing photolithography steps. Multiple mask openings 17 extend through the photoresist mask 16 for exposure of the underlying feature layer 14 to an etching process. During the alignment and exposure step, the BARC layer 18 minimizes reflection of monochromatic light from the underlying feature layer 14 to areas of the photoresist mask 16 which are shielded by a mask or reticle, and thus, are not to be exposed to light. The feature layer 14 may be a polysilicon layer which is patterned to form a gate using conventional fabrication techniques, for example. Alternatively, the feature layer 14 may be a metal conductive layer or a dielectric layer which will be etched and subsequently filled with metal to form a metal conducting line.
As shown in FIG. 1B, the BARC layer 18 is initally etched according to the pattern of the photoresist mask 16. Next, as shown in FIG. 1C, the underlying feature layer 14 is etched, according to the pattern of the photoresist mask 16, to form feature openings 15 that correspond in size and position to the mask openings 17. Accordingly, areas of the feature layer 14 exposed to the etchant through the mask openings 17 are etched, whereas areas of the feature layer 14 which are covered by the photoresist mask 16 are protected from the etchant and remain intact. During the etch process, the photoresist mask 16 is progressively etched and gradually decreases in thickness. Finally, as shown in FIG. 1D, the photoresist mask 16 is stripped from the underlying BARC layer 18. The BARC layer 18 may also be removed from the feature layer 14.
At the photolithography alignment and exposure step, in which the photoresist mask 16 is exposed to monochromatic light through a mask or reticle (not shown) to transfer the desired feature pattern to the photoresist mask 16, some of the light is reflected from the feature layer 14 to areas of the photoresist mask 16 which are covered by the mask or reticle. This causes light wave reflection and interference in the photoresist mask 16, resulting a phenomenon known as standing waves in the cross-sectional profile of the photoresist mask 16.
While the BARC layer 18 minimizes the effect of standing waves in the photoresist mask 16, the occurrence of standing waves remains particularly problematic in deep-UV (DUV) resists because many materials are more reflective at the shorter DUV wavelengths. As a result of the weak etching resistance of 193 nm and 157 nm photoresists, after the exposure and development step the sidewalls of the mask openings 17 exhibit striations of overexposed and underexposed areas. During the etch process, the presence of striations in the photoresist mask 16 frequently causes the profile of the remaining photoresist mask 16 to become tilted or otherwise distorted. This compromises resist selectivity, substantially degrades the resolution of the image in the photoresist mask 16 and, in turn, distorts the feature pattern image etched in the underlying feature layer 14, as shown in FIG. 1D. Accordingly, a novel method is needed to reduce the striation or tilting effect in the sidewalls of mask openings in a resist mask in order to improve resist selectivity, prevent or minimize tilting or bending of the resist profile and enhance the resolution of an image etched in a feature layer.
Accordingly, an object of the present invention is to provide a novel method for reducing the effects of standing waves in a resist mask.
Another object of the present invention is to provide a novel method which reduces striations in sidewalls of mask openings in a resist mask to enhance resist selectivity.
Still another object of the present invention is to provide a novel method which enhances the integrity and structural strength of a resist mask.
Yet another object of the present invention is to provide a novel method which maintains or improves CD uniformity in a resist mask.
A still further object of the present invention is to provide a novel in-situ plasma treatment method which enhances the resolution of a circuit pattern image transferred from a resist mask to a feature layer on a substrate.
Yet another object of the present invention is to provide a novel in-situ plasma treatment method which includes subjecting a photoresist mask to a photoresist-strengthening plasma before or during an etching process.